Testing has thrown up some bugs that we are working on fixing:
* SP,PC,LR not supported as ARM core register names
* "R" prefix should be optional for an ARM core register, supporting existing syntax
(We are verifying this doesn't cause other issues with similar pattern variations, leading to syntax errors)
(The pattern table order will have to be updated to ensure bad-register errors occur at the correct time)
* LDR reg,<expr> not working due to missing pattern variation
(<lbl> will be a new op name in the pattern tables to support an R15 based offset matching <#+-10>)
I suspect there will be more as there are a lot of (perfectly necessary) assembler directives that add complexity to the otherwise fairly simple syntax.
