Another update to the VFP Assembler today with release 0.03.
* Fixed optional data-type variations - ARM p285
(Note the use of multiple data-types is still not supported)
* Removed need to set sz in internal tables for F64/F32 variations)
* Fixed use of register lists in VTBL
* Other minor improvements to code and documentation
The official blog of TBA Software back from the dead after 12 years away from the Acorn RISC OS computing scene
Tuesday, 12 July 2011
Monday, 11 July 2011
VFP Assembler Update
Shortly after 0.01 comes version 0.02 of the VFP/SIMD assembler with a number of bug fixes:
* Fixed VLDR/VSTR <reg>,<expr> not supported
* Fixed SP,LR,PC ARM register names
* Fixed user integer without R# prefix for ARM register numbers
* Other minor fixes
* Updates to documentation and release notes
Tested with the TestVFP script and a manual scan of output created by ObjAsm / DecAof
(Note the BASIC version in VFPLib supports the VLDR fix but not the ARM register names)
* Fixed VLDR/VSTR <reg>,<expr> not supported
* Fixed SP,LR,PC ARM register names
* Fixed user integer without R# prefix for ARM register numbers
* Other minor fixes
* Updates to documentation and release notes
Tested with the TestVFP script and a manual scan of output created by ObjAsm / DecAof
(Note the BASIC version in VFPLib supports the VLDR fix but not the ARM register names)
VFP assembler known bug list
Testing has thrown up some bugs that we are working on fixing:
* SP,PC,LR not supported as ARM core register names
* "R" prefix should be optional for an ARM core register, supporting existing syntax
(We are verifying this doesn't cause other issues with similar pattern variations, leading to syntax errors)
(The pattern table order will have to be updated to ensure bad-register errors occur at the correct time)
* LDR reg,<expr> not working due to missing pattern variation
(<lbl> will be a new op name in the pattern tables to support an R15 based offset matching <#+-10>)
I suspect there will be more as there are a lot of (perfectly necessary) assembler directives that add complexity to the otherwise fairly simple syntax.
* SP,PC,LR not supported as ARM core register names
* "R" prefix should be optional for an ARM core register, supporting existing syntax
(We are verifying this doesn't cause other issues with similar pattern variations, leading to syntax errors)
(The pattern table order will have to be updated to ensure bad-register errors occur at the correct time)
* LDR reg,<expr> not working due to missing pattern variation
(<lbl> will be a new op name in the pattern tables to support an R15 based offset matching <#+-10>)
I suspect there will be more as there are a lot of (perfectly necessary) assembler directives that add complexity to the otherwise fairly simple syntax.
Wednesday, 6 July 2011
Using Functions within VFP/SIMD instructions
Having reviewed the documentation supplied with the 0.01 release, one thing that isn't clear is the way in which expressions are supported within the VFP/SIMD syntax. This will be corrected in the next release.
Register Numbers
<type>#<expression>
Register numbers are a special case where the register type must be specified. So where an ARM register can be simply specified as a number from 0-15, a Single/Double/Quad register must be prefixed by S,D or Q, and then a # followed by the expression. For example Q#FNregister or D#(A%+B%)
Immediate constants
#<expression>
The same as for the standard ARM assembler, subject to encoding limitations as specified in ARM. For a full 32bit or 64bit number, an 8bit constant can be shifted around and duplicated in 9 different ways. For example #&FF, #&FF00, and #&FF00FF00 will encode for VMOV where as #&10F will not.
Immediate floating point or 64bit integers
#F32.<expression>
#F64.<expression>
#I64.<expression>
The special constructors take a number from 0-255 from <expression> and pass it through in raw form to the instruction encoding. This is not particularly useful but completes the syntax. We would recommend using other methods to define constants of these types.
Scalar Offsets
[<expression>]
Hopefully that helps to explain how things work. Good luck to anyone who is testing the assembler and we look forward to some feedback in due course.
Register Numbers
<type>#<expression>
Register numbers are a special case where the register type must be specified. So where an ARM register can be simply specified as a number from 0-15, a Single/Double/Quad register must be prefixed by S,D or Q, and then a # followed by the expression. For example Q#FNregister or D#(A%+B%)
Immediate constants
#<expression>
The same as for the standard ARM assembler, subject to encoding limitations as specified in ARM. For a full 32bit or 64bit number, an 8bit constant can be shifted around and duplicated in 9 different ways. For example #&FF, #&FF00, and #&FF00FF00 will encode for VMOV where as #&10F will not.
Immediate floating point or 64bit integers
#F32.<expression>
#F64.<expression>
#I64.<expression>
The special constructors take a number from 0-255 from <expression> and pass it through in raw form to the instruction encoding. This is not particularly useful but completes the syntax. We would recommend using other methods to define constants of these types.
Scalar Offsets
[<expression>]
Hopefully that helps to explain how things work. Good luck to anyone who is testing the assembler and we look forward to some feedback in due course.
BBC BASIC with VFP/SIMD Assembler Released
Release 0.01 of BBC BASIC with the VFP/NEON (SIMD) assembler is now available to download
This is an Alpha release and is for some initial testing prior to inclusion in the official ROOL source code. It is supplied in a TBAFS archive (naturally) so you'll need !TBAFS to extract it. Documentation is included so please refer to that for further information.
After loading the new BBC BASIC module, to use it you simply write VFP/SIMD instructions like you would any other. You will need to set-up a VFP context using the VFPSupport module before VFP/SIMD instructions will run. We have included an example of this via a BASIC support library that simplifies this process.
We are just starting to use the VFP/SIMD instruction set to re-write part of TAG. Our testing of the assembler will continue as this development progresses.
Sunday, 3 July 2011
BASIC Assembler with VFP/SIMD (finally)
The VFP and SIMD extensions to the BBC BASIC assembler are working! All of the instructions assemble from the test script. Significantly more testing is required before a first release but I hope to publish something to the TBA downloads area in the not too distant future.
There are a few alterations to the official ARM syntax in order to accommodate the legacy BBC BASIC tokens and language syntax
1) In order to use an expression for a register number you have to specify the type followed by # and then an expression - for example Q#FNregister specifies a Quadword type register with a number returned from FNregister.
2) VDUP is currently renamed to VDPL as VDU is a keyword and VDUP.16 will get tokenized as VDUPRINT16 due to existing tokens.
3) Full encoding of floating point or 64bit immediate constants isn't supported, so there is a workaround where you can specify the immediate byte with a I64. F64. or F32. prefix. This assumes you have encoded the value in a suitable way yourself which is better than nothing. It must be said these immediate values are not exactly useful anyway.
3) Full encoding of floating point or 64bit immediate constants isn't supported, so there is a workaround where you can specify the immediate byte with a I64. F64. or F32. prefix. This assumes you have encoded the value in a suitable way yourself which is better than nothing. It must be said these immediate values are not exactly useful anyway.
4) The optional AL condition isn't supported on the unconditional SIMD instructions, and additional register type specifiers following the data-type are also not supported.
There are probably a few more options in the ARM syntax that are not supported - I'll have a go at reading through it all again to create some releases notes.
The to-do list
Error handling is still not integrated fully although this will be looked at next. The current error numbers need evaluation to see how to include some additional VFP related messages. I also expect there to be bugs (or undefined results) relating to use of incorrect syntax, and bugs relating to validation as it isn't possible to test every single invalid combination. The current known bug list includes small things like optional brackets with a single register in a list, and specifying D0-D3 instead of D0,D1,D2,D3 on the VLDx/VSTx instructions. Nothing major.
The final task is updating the help messages and creating some documentation so that the new instructions appear on the various help commands such as HELP [. I'm also looking at adding a new command to display the VFP/SIMD assembler version and some debugging data to help with bug reporting. The documentation will describe how the assembler and pattern tables work, along with how the BASIC version works that generates the optimized pattern tables for the assembler version.
It is quite easy to add additional non VFP/SIMD instructions to the pattern tables although I haven't started to look at what is currently missing.
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